S R Latch Notes

When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR logic gates. The stored bit is present on the output marked Q.

1. Sr Latch Notes Template
2. Sr Latch Notes Definition
3. Sr Latch Example
4. Sr Latch Notes Meaning
5. Sr Latch Schematic

• This is the first in a series of computer science videos about latches and flip-flops. These bi-stable combinations of logic gates form the basis of compute.
• ‹Note that the internal latch inputs will both go from 1 to 0 if the S and R inputs are both 1 when the clock goes low. Hence we must never have S and R at 1 when the clock is 1. ‹We make the following rules for changing inputs. ZDon't change the inputs while the clock is asserted.

While the S and R inputs are both low, feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R (Reset) is held low, then the Q output is forced high, and stays high when S returns to low; similarly, if R is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.

The S-R Latch block is an abstracted behavioral model of a set-reset latch. It does not model the internal individual MOSFET devices (see Assumptions and Limitations for details). Therefore, the block runs quickly during simulation but retains the correct I/O behavior. This HIGH LOW enable signal is applied to the gated latch in the form of clocked pulses. So, gated S-R latch is also called clocked S-R Flip flop or synchronous S-R latch.Since this latch responds to the applied inputs only when the level of the clock pulse is high, this type of flip-flop is also called level triggered flip flop. The logical circuit of a Gated SR Latch or Clocked SR Flip-Flop is shown below.

R-S flip flop D flip flop J-K flip flop T flip flop; S-R Flip Flop. The S-R flip-flop is basic flip-flop among all the flip-flops. All the other flip flops are developed after SR-flip-flop. SR flip flop is represented as shown below. S-R stands for SET and RESET. This can also be called RS flip-flop. Difference is RS is inverted SR flip-flop.

The truth table and diagram

The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates then output 0s, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or 0 depending on the propagation time relations between the gates (a race condition). In certain implementations, it could also lead to longer ringings (damped oscillations) before the output settles, and thereby result in undetermined values

Notes

• The green switch is a on/off switch (similar to a room light switch).
• Q₀ is the previous state of Q and Q₀ is the previous state of Q.
• R and S are asynchronous inputs - that is the output responds to these input immediately. They are active high inputs. Click on their respective green switches and observe.
• S sets the output to 1 and R resets the output to 0.
• Both R and S cannot be high at the same time - the output is undefined.
• Simulate and Breadboard the SR NOR circuit.
• Watch the video to learn how to edit the input (thick) waveforms.

The JK Flip Flop is the most widely used flip flop. It is considered to be a universal flip-flop circuit. The sequential operation of the JK Flip Flop is the same as for the RS flip-flop with the same SET and RESET input.

The difference is that the JK Flip Flop does not the invalid input states of the RS Latch (when S and R are both 1). The JK Flip Flop name has been kept on the inventor name of the circuit known as Jack Kilby.

The basic symbol of the JK Flip Flop is shown below:

The basic NAND gate RS flip-flop suffers from two main problems.

• Firstly, the condition when S = 0 and R = 0 should be avoided.
• Secondly, if the state of S or R changes its state while the input which is enabled is high, the correct latching action does not occur.

Thus to overcome these two problems of the RS Flip-Flop, the JK Flip Flop was designed.

The JK Flip Flop is basically a gated RS flip flop with the addition of the clock input circuitry. When both the inputs S and R are equal to logic “1”, the invalid condition takes place.

Thus, to prevent this invalid condition, a clock circuit is introduced. The JK Flip Flop has four possible input combinations because of the addition of the clocked input. The four inputs are “logic 1”, ‘logic 0”. “No change’ and “Toggle”.

The circuit diagram of the JK Flip Flop is shown in the figure below:

The S and R inputs of the RS bistable have been replaced by the two inputs called the J and K input respectively.

Here J = S and K = R. The two-input AND gates of the RS flip-flop is replaced by the two 3 inputs NAND gates with the third input of each gate connected to the outputs at Q and Ǭ. This cross-coupling of the RS Flip-Flop is used to produce toggle action. As the two inputs are interlocked.

Sr Latch Notes Template

If the circuit is in the “SET” condition, the J input is inhibited by the status 0 of Q through the lower NAND gate. Similarly, the input K is inhibited by 0 status of Q through the upper NAND gate in the “RESET” condition.

When both J and K are at logic “1”, the JK Flip Flop toggle.

The Truth Table of the JK Flip Flop is shown below.

Sr Latch Notes Definition

JK Flip Flop is similar to RS flip flop with the feedback which enables only one of its input terminals. It eliminates the invalid condition which arises in the RS flip flop and put the input terminal either to set or reset condition one at a time.

When both the J and K inputs are at logic “1” at the same time and the clock input is pulsed HIGH, the circuit toggle from its SET state to a RESET or visa versa. When both the terminals are HIGH the JK flip-flop acts as a T type toggle flip-flop.

JK flip-flop has a drawback of timing problem known as “RACE”. The condition of RACE arises if the output Q changes its state before the timing pulse of the clock input has time to go in OFF state.

Sr Latch Example

The timing pulse period (T) should be kept as short as possible to avoid the problem of timing.

Sr Latch Notes Meaning

This condition is not possible always thus a much-improved flip-flop named Master Salve JK Flip Flop was developed. This eliminates all the timing problems by using two RS flip-flop connected in series. One is for the “MASTER “ circuit, which triggers on the leading edge of the clock pulse. The other is called the “SLAVE” circuit, which triggers when the clock pulse is at the falling edge.

Sr Latch Schematic